1. Field of the Invention
The present invention relates to a driver and a driving method, and a display device, and more particularly to a driver and a driving method each of which is capable of more precisely detecting a fault caused on a semiconductor substrate or an insulating substrate having pixel cells disposed in matrix therein, and a display device.
2. Description of the Related Art
In recent years, an active matrix system has been widely adopted in liquid crystal display devices such as a liquid crystal projector device and a liquid crystal display device.
FIG. 1 shows an example of a structure of a semiconductor substrate 10 of a liquid crystal display device adopting the active matrix system.
The semiconductor substrate 10 shown in FIG. 1 is provided with a display circuit 11, a data line driving circuit 12, and a gate line driving circuit 13. Note that, a portion about display of a region having nine pixels in total within a screen in which three pixels are horizontally disposed and three pixels are vertically disposed is described with reference to FIG. 1 for the sake of convenience of the description. However, any other portion about display is structured similarly to the case of the portion about display shown in FIG. 1.
The display circuit 11 is structured such that pixel cells 21-1 to 21-9 are disposed in matrix within the screen in which three pixel cells are horizontally disposed, and three pixel cells are vertically disposed. It is noted that when there is no necessity for individually distinguishing the pixel cells 21-1 to 21-9 from one another in the following description, the pixel cells 21-1 to 21-9 are collectively referred to as “the pixel cells 21”.
The pixel cells 21 are connected to the data line driving circuit 12 through data lines Dn−1, Dn and Dn+1 (n: odd number), respectively, which are disposed in parallel on the semiconductor substrate 10 so as to be insulated from one another. Here, a suffix added to D represents what number the data line concerned belongs to in a direction from a left-hand side to a right-hand side in the figure (in a horizontal direction in the figure).
In addition, the pixel cell 21 is connected to the gate line driving circuit 13 through corresponding one of gate lines Gm−1, Gm and Gm+1 (m: odd number) which are disposed in parallel on the semiconductor substrate 10 so as to be electrically insulated from the data lines Dn−1, Dn and Dn+1 and so as to make right angles to the data lines Dn−1, Dn and Dn+1. Here, a suffix added to G represents what number the data line concerned belongs to in a direction from an upper side to a lower side in the figure (in a vertical direction in the figure).
It is noted that when there is no necessity for individually distinguishing the data lines Dn−1, Dn and Dn+1 from one another in the following description, the data lines Dn−1, Dn and Dn+1 are collectively referred to as “the data lines D”, and also when there is no necessity for individually distinguishing the gate lines Gm−1, Gm and Gm+1 from one another in the following description, the gate lines Gm−1, Gm and Gm+1 are collectively referred to as “the gate lines G”.
The pixel cell 21-1 is composed of a switch 31, an electrode 32, and a capacitor 33. The switch 31, for example, is constituted by a field effect transistor (FET). A gate of the switch 31 is connected to the gate line Gm−1, and a drain thereof is connected to the data line Dn−1. In addition, a source of the switch 31 is connected to each of the electrode 32 and one end of the capacitor 33, and the other end of the capacitor 33 is connected to a common electrode.
In the pixel cell 21-1, when the switch 31 is turned ON by drive of the gate line Gm−1, the charges are accumulated in the capacitor 33 based on a potential of a signal which is inputted to the switch 31 by drive of the data line Dn−1. That is to say, data is written to the capacitor 33. Also, the switch 31 is turned OFF by stopping the drive of the gate line Gm−1, so that the capacitor 33 holds therein data thus written thereto.
At this time, a potential Pm−1n−1 at the electrode 32 is one developed at the one terminal of the capacitor 33 connected to that electrode 32. A liquid crystal held between the semiconductor substrate 10 and a counter substrate (not shown) makes a response to be exited in correspondence to a difference between the potential Pm−1n−1 and a potential of the counter substrate. Here, the counter substrate is a semiconductor substrate which is disposed so as to face the semiconductor substrate 10, and which has the common electrode. As a result, the pixel corresponding to the pixel cell 21-1 is activated for display. It is noted that while a description is omitted here for the sake of simplicity, each of the pixel cells 21 other than the pixel cell 21-1 is structured similarly to the case of the pixel cell 21-1 and similarly operates.
The data line driving circuit 12, for example, is provided with a shift register and the like. The data line driving circuit 12 successively shifts data which is inputted thereto from the outside every horizontal line to scan the data lines D in the horizontal direction, thereby successively driving the data lines D.
The gate line driving circuit 13, for example, is provided with a shift register and the like. The gate line driving circuit 13 successively shifts data which is inputted thereto for control for the scanning from the outside, thereby successively driving the gate lines Gm−1, Gm and Gm+1 every period of time for the horizontal scanning. As a result, the switches 31 of the pixel cells 21 are turned ON in order in units of the switches 31 of the pixel cells 21 disposed in the horizontal direction, so that a horizontal line as a scanning object moves vertically.
The data line driving circuit 12 and the gate line driving circuit 13 carry out the drive in the manner as described above, which results in that the data is successively written to the capacitors 33 of the pixel cells 21 to excite the liquid crystal, thereby displaying a desired image on the screen.
Now, in such a semiconductor substrate, a line fault such as short circuit or disconnection may be caused in manufacturing processes. For this reason, it is inspected whether or not the line fault is caused on the semiconductor substrate in the manufacturing processes.
FIG. 2 shows an example of a structure of a semiconductor substrate 40 which is provided with a detection circuit for detecting a fault for the inspection. It is noted that the same constituent elements as those shown in FIG. 1 are designated with the same reference numerals, respectively, and a repeated description thereof is omitted here for the sake of simplicity.
In the semiconductor substrate 40, a detection circuit 41 is provided across the display circuit 11 from the data line driving circuit 12.
The detection circuit 41 detects the line fault caused on the semiconductor substrate 40 by utilizing a predetermined detecting method. The following detecting method, for example, is known in the art as this detecting method. That is to say, an AND gate is provided as a detection circuit, and a signal having a predetermined potential is applied across adjacent two data lines or gate lines. Also, the line fault caused on the semiconductor substrate 40 is detected based on a logical product of logical values corresponding to potentials of the adjacent two data lines or gate lines after application of the signal having the predetermined potential across them. This detecting method, for example, is described in Japanese Patent Laid-Open No. 2005-43661.
In addition, another detecting method is known in the art as follows. That is to say, the line fault caused on the semiconductor substrate 40 is detected based on a change in potential before and after an operation for reading out charges accumulated in the capacitor 33 in a phase of write of data to the data line D which has an arbitrary voltage applied thereto, and which is set in a high impedance state.
However, the recent liquid crystal display devices for which a high definition is advanced involve the following problem. That is to say, a ratio of a capacity of the capacitor 33 to a parasitic capacity of the data line is equal to or larger than 1:200. Also, the potential change before and after the reading-out operation is minute. As a result, the detection results are readily influenced by noises.
In order to cope with this problem, there is also devised a detecting method of detecting a line fault caused on a semiconductor substrate based on a comparison of potential changes, before and after an reading-out operation, appearing across adjacent two data lines or gate lines.